Voltage sustaining layer wiht opposite-doped island for seminconductor power devices

ABSTRACT

A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of co-pending U.S. patent applicationSer. No. 12/355,165, filed Jan. 16, 2009; which is a divisionalapplication of U.S. patent application Ser. No. 11/838,522, filed Aug.14, 2007, now U.S. Pat. No. 7,498,614; which is a continuation of U.S.patent application Ser. No. 11/365,223, filed Mar. 1, 2006, now U.S.Pat. No. 7,271,067; which is a divisional application of U.S. patentapplication Ser. No. 10/860,435, filed Jun. 3, 2004, now U.S. Pat. No.7,227,197; which is a divisional application of U.S. patent applicationSer. No. 10/382,027, filed Mar. 5, 2003, now U.S. Pat. No. 6,936,867;which is a divisional application of U.S. patent application Ser. No.08/953,077, filed Oct. 17, 1997, now U.S. Pat. No. 6,635,906; which is acontinuation of U.S. patent application Ser. No. 08/598,386, filed Feb.8, 1996, now abandoned; which is a continuation of U.S. patentapplication Ser. No. 08/268,339, filed Jun. 30, 1994, now abandoned.

BACKGROUND OF THE INVENTION

This invention relates to semiconductor high voltage devices, andspecifically to semiconductor high voltage devices with a voltagesustaining layer containing floating regions.

It is well-known that in many semiconductor devices, such as VD-MOST andSIT, a high sustaining voltage always accompanies a high specificon-resistance. This is due to the fact that, for a high sustainingvoltage, thickness of a voltage sustaining layer should be large anddoping concentration of the voltage sustaining layer should be low, soas the peak field does not exceed the critical field for breakdown−E_(C), which is normally expressed by E_(C)=8.2×10⁵×V_(B) ^(−0.2) V/cmfor silicon, where V_(B) is the breakdown voltage of the voltagesustaining layer.

In a uniformly doped n-type voltage sustaining layer between p+-regionand n+-region, in order to obtain a minimum specific on-resistance at agiven breakdown voltage, a doping concentration N_(D) and a thickness Wof the voltage sustaining layer are optimized such that a maximum fieldis at p+-n-junction and its value is equal to E_(C), a minimum field isat n+-n-junction and equal to E_(C)/3. For a silicon device,

N _(D)=1.9×10¹⁸ ×V _(B) ^(−1.4) cm⁻³  (1)

W=1.8×10⁻² ×V _(B) ^(−1.2) ÿm ⁻²  (2)

(see, e.g., P. Rossel, Microelectron. Reliab., vol. 24, No. 2, pp339-366, 1984).

For the VDMOST shown in FIG. 1A, a field profile in the voltagesustaining layer at V_(B) is shown in FIG. 1B, where a slope of thefield versus distance is qN_(D)/E_(s), E_(s) is the permittivity of thesemiconductor and q is the electron charge. The change of field throughthe n-region is qN_(D)/E_(s), 2E_(C)/3. The relation between R_(on) andV_(B) of a n-type voltage sustaining layer is then expressed by

R _(on) =W/qÿÿ _(n) N _(D)=0.83×10⁻⁸ ×V _(B) ^(2.5) ÿ.cm²  (3)

where ÿ_(n) is the mobility of the electron and ÿ_(n)=710×V_(B) ^(0.1)cm/V.sec is used for silicon.

In order to get even lower R_(on) at a given V_(B), some research hasbeen done to optimize the doping profile instead of using a uniformdoping, see: [1] C. Hu, IEEE Trans. Electron Devices, vol. ED-2, No. 3,p243 (1979); [2] V. A. K. Temple et al., IEEE Trans. Electron Devices,vol. ED-27, No. 2, p243 (1980); [3] X. B. Chen, C. Hu, IEEE Trans.Electron Devices, vol. ED-27, No. 6, p985-987 (1982). However, theresults show no significant improvement.

BRIEF SUMMARY OF THE INVENTION

The purpose of this invention is to provide a semiconductor high voltagedevice having a new voltage sustaining layer with better relationshipbetween R_(on) and V_(B). To achieve the above purpose, a semiconductorhigh voltage device is provided, which comprises a substrate of a firstconductivity type, at least one region of a second conductivity type,and a voltage sustaining layer of the first conductivity type having aplurality of discrete floating (embedded) islands of a secondconductivity type between said substrate and said region of the secondconductivity type.

According to this invention, an n (or p) type voltage sustaining layeris divided by (n−1) planes into n sub-layers with equal thickness, and p(or n) type discrete floating islands are introduced with theirgeometrical centers on such planes. The average dose N_(T) of thefloating islands in each plane is about 2E_(s)Ec/3q. For silicon,

N _(T)=2E _(s) E _(c)/3q=3.53×10¹² V _(B) ^(−0.2) cm⁻²  (4)

With such a floating island, the field is reduced by an amount about2E_(C)/3 from a maximum value E_(C) at a side of the floating island toa minimum value E_(C)/3 at another side of the floating island so far asthe floating island is fully depleted. Each sub-layer is designed tosustain a voltage of V_(B1)=V_(B)/n, and to have a thickness and dopingconcentration which are almost the same as those form formulas (1) and(2) with V_(B) is replaced by V_(B1), so that when a reverse voltagewhich is about the breakdown voltage V_(B) is applied over the wholevoltage sustaining layer, the maximum field is E_(C) and the minimumfield is E_(C)/3, where the locations of the maximum field are not onlyat the p+-n (or n+-p) junction, but also at the points of each p (or n)island nearest to the n+-n (or p+-p) junction; the locations of theminimum field are not only at the n+-n (or p+-p) junction, but also atthe points of each p (or n) islands nearest to the p+-n (or n+-p)junction. An example of the structure of a VDMOST using a voltagesustaining layer of this invention with n=2 is shown in FIG. 3A and thefield profile under a reverse voltage of V_(B) is shown in FIG. 3B.Apparently, in such a condition, V_(B)=2WE_(C)/3, where W is the totalthickness of the voltage sustaining layer.

It is easy to prove that the above structured voltage sustaining layerincluding a plurality of floating regions is fully depleted under areverse bias voltage about V_(B)/2. The flux due to the charges of theionized donors (or acceptors) under the p (or n) islands are almosttotally terminated by the charges of the p (or n) islands. The maximumfield is then 2E_(C)/3 and the minimum field is zero, the locations ofthe maximum field are the same as those under a reverse bias voltage ofV_(B).

Apparently, the p (or n) islands make the field not to be accumulatedthroughout the whole voltage sustaining layer. For a given value ofbreakdown voltage V_(B), the doping concentration N_(D) can be higherthan that in a conventional voltage sustaining layer and the specificon-resistance is much lower than that in a conventional voltagesustaining layer.

Suppose that there are n sub-layers in a voltage sustaining layer. Then,each sub-layer can sustain a voltage of V_(B)/n, where V_(B) is thebreakdown voltage of the total voltage sustaining layer. Obviously,instead of (3), the relation of R_(on) and V_(B) of this invention is

R _(on) =n×0.83×10⁻⁸(V _(B) /n)^(2.5) ÿ.cm²=0.83×10⁻⁸ V _(B) ^(2.5) /n^(1.5) ÿ.cm²  (5)

Compared to formula (3), it can been seen that the on-resistance of avoltage sustaining layer having n sub-layers is much lower than that ofa conventional one.

The inventor has experimented and obtained remarkable results, whichshow that the on-resistance of a semiconductor device using a voltagesustaining layer with n=2 of this invention is at least lower than ½ ofthat of a conventional one with the same breakdown voltage, although thereal value of R_(on) of a voltage sustaining layer having floatingislands is a little higher than the value calculated from expression (5)when n<3, due to the effect that the current path is narrowed by thep-type floating islands. Besides, for minimizing R_(on), the optimumvalue of N_(T) is slightly different with the expression (4), due tothat the negative charges of p-type floating islands are concentrated inthe p-regions instead of being uniformly distributed on a plane, whereasthese negative charges are used to absorb the flux of ionized donorsbelow that plane.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The foregoing summary, as well as the following detailed description ofthe invention, will be better understood when read in conjunction withthe appended drawings. For the purpose of illustrating the invention,there are shown in the drawings embodiments which are presentlypreferred. It should be understood, however, that the invention is notlimited to the precise arrangements and instrumentalities shown. In thedrawings:

FIG. 1 is the schematic diagram of a prior art VDMOST, where FIG. 1Ashows the structure and FIG. 1B shows the field profile.

FIG. 2 shows a voltage sustaining layer structure of this invention,where FIG. 2A shows a voltage sustaining layer structure with islands inone plane. FIGS. 2B and 2C show the structures of the voltage sustaininglayer with the floating islands in two planes.

FIG. 3 shows the structure and the field profile of a VDMOST with thevoltage sustaining layer of this invention. In FIG. 3A, the voltagesustaining layer of FIG. 2A is used. The field profile of this structureunder a reverse voltage of V_(B) is shown in FIG. 3B. In FIG. 3C, avoltage sustaining layer of FIG. 2C is used.

FIG. 4 shows the structure of an IGBT with a voltage sustaining layer ofthis invention. In FIG. 4A, a voltage sustaining layer of FIG. 2A isused. In FIG. 4B, a voltage sustaining layer of FIG. 2C is used.

FIG. 5 shows a structure of a RMOST with the voltage sustaining layer ofthis invention shown in FIG. 2A.

FIG. 6 shows a structure of a bipolar junction transistor with thevoltage sustaining layer of this invention shown in FIG. 2A.

FIG. 7 shows a structure of a SIT with the voltage sustaining layer ofthis invention shown in FIG. 2A.

DETAILED DESCRIPTION OF THE INVENTION

All the structures schematically shown in the figures are ofcross-sectional view. In FIGS. 3-7, the same numeral designates similarparts of a high voltage semiconductor device, where, 1 designates p (orn) island in the voltage sustaining layer; 3 designates n+ (or p+)substrate; 4 designates p (or n) source body; 5 designates n+ (or p+)source; 6 designates p+ (or n+) substrate; 7 designates n (or p) bufferlayer; 8 designates p+ (or n+) outer base of BJT; 9 designates p+ (orn+) grid of SIT; and shaded regions designate oxide regions.

FIG. 2 shows several structures of a voltage sustaining layer accordingto the invention.

In FIG. 2A, a voltage sustaining layer with p (or n) islands in a planeis shown (i.e., n=2, two sub-layers). In FIG. 2B, a voltage sustaininglayer with p (or n) islands disposed in two planes is shown (i.e., n=3,three sub-layers), where each island in the upper plane is verticallyarranged over a corresponding island in the lower plane. FIG. 2C showsanother voltage sustaining layer with two planes of p (or n) islands(n=3), wherein each of the islands in the upper plane is verticallyarranged in the middle of two neighboring islands in the lower plane.

The horizontal layout of the voltage sustaining layer can be eitherinterdigitated (finger), or hexagonal (cell), or rectangular (cell). Inall the figures of schematic cross-sectional view of the structures,only one or two units (fingers or cells) of the voltage sustaining layerare shown.

The voltage sustaining layer of this invention can be used in many highvoltage devices.

-   -   1) High voltage diode

This can be simply realized by forming two electrodes on the p+-regionand the n+-region in any of structures shown in FIG. 2.

-   -   2) High voltage (or power) VDMOST

FIG. 3A shows a structure of a vertical diffusion metal oxidesemiconductor transistor (VDMOS or VDMOST) using the voltage sustaininglayer with a plurality of floating islands disposed in one plane, i.e.,n=2. FIG. 3B shows the field profile along a line through a center ofislands in the voltage sustaining layer and perpendicular to said planesin FIG. 3A. FIG. 3C shows a structure of a VDMOST using a voltagesustaining layer with islands in two planes, i.e., n=3.

The turn-off process of a resultant device is almost as fast as aconventional VDMOST. The turn-on process is like the turn-off process ofa conventional IGBT, which consists of a fast stage and a long tail. Thelong tail is due to the p (or n) islands needing to be charged.

-   -   3) High Voltage (or Power) IGBT

FIG. 4A shows a structure of an IGBT using a voltage sustaining layerwith n=2. FIG. 4B shows a structure of an IGBT using a voltagesustaining layer with n=3. In order to improve the turn-on process of aVDMOST with the voltage sustaining layer of this invention, only a smallamount of minorities is needed to charge the islands in the voltagesustaining layer. This can be done by using an IGBT structure with avery low injection. Investigations by the inventor indicate that aninjection ratio of less than 0.1 is enough to make the turn-on processto be almost as fast as the turn-off process and results in no longtail. The low injection ratio makes the device operate dominantly by themajority carriers.

-   -   4) High Voltage (or Power) RMOST

FIG. 5 shows a structure of an RMOST using a voltage sustaining layer ofthis invention, where n=2.

-   -   5) High Voltage (or Power) BJT

FIG. 6 shows a structure of a bipolar junction transistor using avoltage sustaining layer of this invention, where n=2.

-   -   6) High Voltage (or Power) SIT

FIG. 7 shows a structure of a static induction transistor using avoltage sustaining layer of this invention, where n=2.

The design references of a voltage sustaining layer of this inventionmay be calculated according to above formulas for calculating E_(C) andthe average dose of the islands in a plane. For example, at first, avalue of a desirable breakdown voltage V_(B) is determined, and thevalue of E_(C) is calculated from the determined E_(C). Then, from thetechnology achievable number of sub-layers n, the lateral size of a unitand the width of the islands in a plane, the number of impurity atoms ineach island is calculated. The calculated values can be used as thereference values for simulation in CAD if more accurate values areneeded.

An example of a process for making a vertical n-IGBT using the voltagesustaining layer of this invention is stated briefly as follows:

-   -   First step: preparing a wafer of a p+-substrate having an        n+-buffer on it;    -   Second step: forming a n-epilayer on said wafer;    -   Third step: growing a thin oxide layer on the epilayer and        forming openings by photo-lithograph;    -   Fourth step: implanting boron through the openings for making        p-islands and then removing the oxide layer;    -   Fifth step: repeat (n−1) times of second step to fourth step.    -   The following steps are all the same as fabricating a        conventional IGBT.

Although the invention has been described and illustrated with referenceto specific embodiments thereof, it is not intended that the inventionbe limited to these illustrative embodiments. Those skilled in the artwill recognized that modifications and variations can be made withoutdeparting from the spirit of the invention. Therefore, it is intendedthat this invention encompass all such variations and modifications asfall within the scope of the appended claims.

I claim:
 1. A method of manufacturing a semiconductor device having avoltage sustaining layer with n sub-layers, n being an integer greaterthan or equal to 2, the method comprising: (a) preparing a semiconductorwafer having first and second main surfaces and a region of a firstconductivity type proximate the first main surface; (b) forming anepitaxial layer of the first conductivity type on the first main surfaceof the semiconductor wafer; (c) growing an oxide layer on the epitaxiallayer; (d) forming at least one opening in the oxide layer; (e)implanting a dopant through the at least one opening to form at leastone region of a second conductivity type; (f) removing the oxide layer;and (g) repeating steps (b)-(f) n−1 times, the voltage sustaining layerhaving a width W extending from the first main surface of thesemiconductor wafer, such that the at least one region of the secondconductivity type of a sub-layer k is spaced from the first main surfaceof the semiconductor wafer by a distance of kW/n.
 2. The method of claim1, wherein the at least one region of the second conductivity type inone of the n sub-layers is offset in a direction parallel to the firstmain surface of the semiconductor wafer with respect to the at least oneregion of the second conductivity type in an adjacent sub-layer
 3. Themethod of claim 1, wherein the at least one region of the secondconductivity type in one of the n sub-layers is aligned in a directionparallel to the first main surface of the semiconductor wafer with theat least one region of the second conductivity type in an adjacentsub-layer
 4. The method of claim 1, wherein step (a) comprises forming abuffer layer of the first conductivity type on a substrate of the secondconductivity type.
 5. The method of claim 1, wherein the firstconductivity type is one of n-type and p-type and the secondconductivity type is the other of n-type and p-type.
 6. The method ofclaim 1, wherein the first region of the first conductivity type has afirst doping concentration and the epitaxial layer of the firstconductivity type has a second doping concentration different from thefirst doping concentration.